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K6X4008C1F Family
Document Title
512Kx8 bit Low Power full CMOS Static RAM
CMOS SRAM
Revision History
Revision No.
0.0 0.1
History
Initial draft Revised - Added Commercial Product. Finalized - Added Lead Free 32-SOP-525 Product - Changed ICC from 10mA to 5mA - Changed ICC1 from 8mA to 7mA - Changed ICC2 from 40mA to 30mA - Changed ISB from 3mA to 0.4mA - Changed IDR(Commercial) from 15A to 12A - Changed IDR(industrial) from 20A to 12A - Changed IDR(Automotive) from 30A to 25A
Draft Date
July 30, 2002 November 30, 2002
Remark
Preliminary Preliminary
1.0
September 16, 2003 Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
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Revision 1.0 September 2003
K6X4008C1F Family
512Kx8 bit Low Power full CMOS Static RAM
FEATURES
* Process Technology: Full CMOS * Organization: 512Kx8 * Power Supply Voltage: 4.5~5.5V * Low Data Retention Voltage: 2V(Min) * Three state output and TTL compatible * Package Type: 32-DIP-600, 32-SOP-525, 32-TSOP2-400F/R
CMOS SRAM
GENERAL DESCRIPTION
The K6X4008C1F families are fabricated by SAMSUNGs advanced full CMOS process technology. The families supports various operating temperature range and various package types for user flexibility of system design. The families also support low data retention voltage for battery backup operation with low data retention current.
PRODUCT FAMILY
Power Dissipation Product Family Operating Temperature Vcc Range Speed Standby Operating (ISB1, Max) (ICC2, Max) 20A K6X4008C1F-F K6X4008C1F-Q Industrial (-40~85C) Automotive (-40~125C) 4.5~5.5V 551)/70ns 30A 30mA PKG Type
K6X4008C1F-B
Commercial (0~70C)
32-DIP-600, 32-SOP-525, 32-TSOP2-400F/R 32-SOP-525, 32-TSOP2-400F
1. The parameter is measured with 50pF test load.
PIN DESCRIPTION
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27
FUNCTIONAL BLOCK DIAGRAM
VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6
VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS I/O1 I/O8
Clk gen.
Precharge circuit.
32-DIP 32-SOP 32-TSOP2 (Forward)
26 25 24 23 22 21 20 19 18 17
32-TSOP2 (Reverse)
7 8 9 10 11 12 13 14 15 16
Row Addresses
Row select
Memory array
Data cont
I/O Circuit Column select
Data cont
Pin Name WE CS OE A0~A18 I/O1~I/O8 Vcc Vss
Function Write Enable Input Chip Select Input Output Enable Input Address Inputs Data Inputs/Outputs Power Ground
CS WE OE
Column Addresses
Control logic
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
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K6X4008C1F Family
PRODUCT LIST
Commercial Products(0~70C) Part Name
K6X4008C1F-DB55 K6X4008C1F-DB70 K6X4008C1F-GB55 K6X4008C1F-GB70 K6X4008C1F-BB551) K6X4008C1F-BB701) K6X4008C1F-VB55 K6X4008C1F-VB70 K6X4008C1F-MB55 K6X4008C1F-MB70 1. Lead Free Product
CMOS SRAM
Industrial Products(-40~85C) Part Name
K6X4008C1F-DF55 K6X4008C1F-DF70 K6X4008C1F-GF55 K6X4008C1F-GF70 K6X4008C1F-BF551) K6X4008C1F-BF701) K6X4008C1F-VF55 K6X4008C1F-VF70 K6X4008C1F-MF55 K6X4008C1F-MF70
Automotive Products(-40~125C) Part Name
K6X4008C1F-GQ55 K6X4008C1F-GQ70 K6X4008C1F-VQ55 K6X4008C1F-VQ70
Function
32-DIP, 55ns, LL 32-DIP, 70ns, LL 32-SOP, 55ns, LL 32-SOP, 70ns, LL 32-SOP, 55ns, LL 32-SOP, 70ns, LL 32-TSOP2-F, 55ns, LL 32-TSOP2-F, 70ns, LL 32-TSOP2-R, 55ns, LL 32-TSOP2-R, 70ns, LL
Function
32-DIP, 55ns, LL 32-DIP, 70ns, LL 32-SOP, 55ns, LL 32-SOP, 70ns, LL 32-SOP, 55ns, LL 32-SOP, 70ns, LL 32-TSOP2-F, 55ns, LL 32-TSOP2-F, 70ns, LL 32-TSOP2-R, 55ns, LL 32-TSOP2-R, 70ns, LL
Function
32-SOP, 55ns, L 32-SOP, 70ns, L 32-TSOP2-F, 55ns, L 32-TSOP2-F, 70ns, L
FUNCTIONAL DESCRIPTION
CS H L L L OE X1) H L X1) WE X1) H H L I/O Pin High-Z High-Z Dout Din Mode Deselected Output disbaled Read Write Power Standby Active Active Active
1. X means dont care.( Must be in low or high state.)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN,VOUT VCC PD TSTG TA Ratings -0.5 to VCC+0.5V(max. 7.0V) -0.3 to 7.0 1.0 -65 to 150 0 to 70 -40 to 85 -40 to 125 C Unit V V W C Remark K6X4008C1F-B K6X4008C1F-F K6X4008C1F-Q
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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K6X4008C1F Family
RECOMMENDED DC OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Min 4.5 0 2.2 -0.5
3)
CMOS SRAM
Typ 5.0 0 Max 5.5 0 Vcc+0.52) 0.8 Unit V V V V
Note: 1.Commercial Product: TA=0 to 70C, otherwise specified Industrial Product: TA=-40 to 85C, otherwise specified Automotive Product: TA=-40 to 125C, otherwise specified 2. Overshoot: VCC+3.0V in case of pulse width 30ns 3. Undershoot: -3.0V in case of pulse width 30ns 4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25C)
Item Input capacitance Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol CIN CIO
Test Condition VIN=0V VIO=0V
Min -
Max 8 10
Unit pF pF
DC AND OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply current Average operating current Symbol ILI ILO ICC ICC1 ICC2 Output low voltage Output high voltage Standby Current(TTL) Standby Current(CMOS) VOL VOH ISB ISB1 VIN=Vss to Vcc CS=VIH or OE=VIH or WE=VIL, VIO=Vss to Vcc IIO=0mA, CS=VIL, VIN=VIL or VIH, Read Cycle time=1s, 100% duty, IIO=0mA CS0.2V, VIN0.2V or VINVcc-0.2V
Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL
Test Conditions
Min -1 -1 2.4 K6X4008C1F-B -
Typ -
Max 1 1 5 7 30 0.4 0.4 20 30
Unit A A mA mA mA V V mA A A
IOL=2.1mA IOH=-1.0mA CS=VIH, Other inputs = VIL or VIH CSVcc-0.2V, Other inputs=0~Vcc
K6X4008C1F-F K6X4008C1F-Q
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K6X4008C1F Family
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level: 0.8 to 2.4V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load (See right): CL=100pF+1TTL CL=50pF+1TTL CL1)
CMOS SRAM
1. Including scope and jig capacitance
AC CHARACTERISTICS
(Vcc=4.5~5.5V, Commercial product: TA=0 to 70C, Industrial product: TA=-40 to 85C, Automotive product: TA=-40 to 125C)
Speed Bins Parameter List Symbol Min Read cycle time Address access time Chip select to output Output enable to valid output Read Chip select to low-Z output Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Output hold from address change Write cycle time Chip select to end of write Address set-up time Address valid to end of write Write Write pulse width Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW 55 10 5 0 0 10 55 45 0 45 40 0 0 25 0 5 55ns Max 55 55 25 20 20 20 Min 70 10 5 0 0 10 70 60 0 60 50 0 0 30 0 5 70ns Max 70 70 35 25 25 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention Data retention current
Symbol
VDR IDR
Test Condition
CSVcc-0.2V K6X4008C1F-B Vcc=3.0V, CSVcc-0.2V K6X4008C1F-F K6X4008C1F-Q
Min
2.0 -
Typ
-
Max
5.5 12 12 25
Unit
V A
Data retention set-up time Recovery time
tSDR tRDR
See data retention waveform
0 5
-
-
ms
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K6X4008C1F Family
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC Address tOH Data Out Previous Data Valid tAA
CMOS SRAM
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC Address tAA tCO1 CS tOE OE tOLZ tLZ Data Valid tOHZ tHZ tOH
Data out
NOTES (READ CYCLE)
High-Z
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.
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K6X4008C1F Family
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC Address tCW(2) CS tAW tWP(1) WE tAS(3) Data in tWHZ Data out Data Undefined tDW Data Valid tOW tDH tWR(4)
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(2) (CS
Controlled)
tWC Address tAS(3) CS tAW tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4)
Data out
NOTES (WRITE CYCLE)
High-Z
High-Z
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
VCC 4.5V tSDR Data Retention Mode tRDR
2.2V VDR CSVCC - 0.2V
CS GND
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Revision 1.0 September 2003
K6X4008C1F Family
PACKAGE DIMENSIONS
32 PIN DUAL INLINE PACKAGE (600mil)
CMOS SRAM
Units : millimeter(Inch)
+0.10 -0.05 0.010+0.004 -0.002
0.25
#32
#17
13.600.20 0.5350.008
#1 42.31 1.666 MAX 41.910.20 1.6500.008
#16 3.810.20 0.1500.008 5.08 0.200 MAX
15.24 0.600
0~15
( 1.91 ) 0.075
0.460.10 0.0180.004 1.520.10 0.0600.004
3.300.30 0.1300.012 2.54 0.100 0.38 MIN 0.015
32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil)
0~8 #32 #17
14.120.30 0.5560.012
11.430.20 0.4500.008
#1 20.87MAX 0.822 20.470.20 0.8060.008
#16 2.740.20 0.1080.008 3.00 0.118 MAX
13.34 0.525
0.20 +0.10 -0.05 0.008+0.004 -0.002
0.800.20 0.0310.008
0.10 MAX 0.004 MAX
+0.100 -0.050 +0.004 0.016 -0.002
( 0.71 ) 0.028
0.41
1.27 0.050
0.05 0.002 MIN
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Revision 1.0 September 2003
K6X4008C1F Family
PACKAGE DIMENSIONS
32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)
CMOS SRAM
Units : millimeter(Inch)
0.25 ( 0.010 ) #32 #17
0~8
0.45 ~0.75 0.018 ~ 0.030
11.760.20 0.4630.008
#1 21.35 MAX 0.841 20.950.10 0.8250.004
#16 1.000.10 0.0390.004 1.20 0.047MAX 0.10 MAX 0.004 MAX 0.15 +0.10 -0.05 0.006 +0.004 -0.002
10.16 0.400
( 0.50 ) 0.020
( 0.95 ) 0.037
0.400.10 0.0160.004
1.27 0.050
0.05 0.002MIN
32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)
( 0.25 ) 0.010 #1 #16
0~8
0.45 ~0.75 0.018 ~ 0.030
11.760.20 0.4630.008
#32 21.35 0.841 MAX 20.950.10 0.8250.004
#17 1.00 0.10 0.0390.004 1.20 0.047 MAX 0.10 MAX 0.004 MAX
+0.10 -0.05 0.006 +0.004 -0.002
10.16 0.400
0.15
( 0.50 ) 0.020
( 0.95 ) 0.037
0.400.10 0.0160.004
1.27 0.050
0.05 0.002MIN
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Revision 1.0 September 2003

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